1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to a synchronization circuit.
2. Related Art
A semiconductor circuit may include a synchronization circuit such as a delay locked loop (DLL) or a duty cycle corrector (DCC) for delay locking or duty cycle correction.
The delay locked loop is used to solve a problem in that an internal clock utilized in a semiconductor integrated circuit is delayed through a clock buffer and a transmission line to cause a phase difference between the internal clock and an external clock and thus an output data access time is increased.
When the duty cycle of a clock signal is distorted, the duty cycle corrector is used to correct the duty cycle.
As a semiconductor integrated circuit operates at ever increasing speeds, accurate delay locked operation and duty cycle correction is desirable.